1. Field of the Invention
The present inventions relates to a display, and more particularly, to a signal transmitting and receiving system and associated timing controller of a display.
2. Description of the Prior Art
In a conventional point-to-point (P2P) timing controller, frame data is transmitted to a plurality of source drivers by using a single data rate. However, using a single data rate to transmit the frame data will cause a high electromagnetic interference (EMI) peak. In addition, because the P2P timing controller uses a Serializer/Deserializer (SerDes) interface to transmit the frame data, and the data rate is very high (e.g. more than 1 Gb/s), therefore, the conventional spread spectrum techniques are difficult to be applied to the P2P timing controller.
In addition, in a display system, the timing controller is connected to the source driver(s) via at least one data channel (data lines) and a lock channel. A voltage level of the lock channel is determined by the source driver, and the timing controller refers to the voltage level of the lock channel to determine to transmit a training signal or a data signal to the source driver. In detail, when the display system is powered on, the voltage level of the lock channel is controlled to correspond to a logic value “0”, the timing controller transmits the training signal to the source driver, and a clock and data recovery (CDR) included in the source driver is used to generate an internal clock by locking frequency and phase according to the training signal from the timing controller. After the source driver confirms that the frequency and phase of the internal clock are locked, the source driver controls the lock channel to have the voltage level corresponds to a logic value “1”. When the voltage level of the lock channel corresponds to the logic value “1”, the timing controller transmits the data signal to the source driver, and the CDR included in the source driver uses the internal clock to sample the data signal to generate recovered data.
In the conventional display system mentioned above, when a data rate of the data signal is changed during the voltage level of the lock channel having the logic value “1”, the CDR may happen a dead lock event and fail to use the internal clock to sample the data signal to generate the correct recovered data.